WEBVTT 00:00.000 --> 00:13.680 So, I know everyone, so I'm Everest, my course I need a 5-0-0. 00:13.680 --> 00:26.000 I work with the Pito-SDR from maybe 6 years now, just curious how many people on Pito-SDR 00:26.000 --> 00:27.000 here. 00:27.000 --> 00:32.000 Okay, right. 00:32.000 --> 00:47.240 Okay, so this presentation is the presentation about what could be an autonomous SDR, which is based 00:47.240 --> 00:52.240 on the same architecture of Pito-SDR. 00:52.240 --> 01:05.200 So just to get back to the basics, generally you use an SDR, like a peripheral. 01:05.200 --> 01:13.760 You can plug it through USB, network, PCA Express, and all the processing is generally done 01:13.760 --> 01:27.120 on the PC, and so you need to install software, depending on your operating system, 01:27.120 --> 01:28.120 on your PC. 01:28.120 --> 01:35.920 So for example, here is a SDR++ client. 01:35.920 --> 01:43.520 The idea here is to have something which is more autonomous, which made that it's not just 01:43.520 --> 01:55.640 an SDR, which is a 9-Q, like with the senior gateway, but try to get it like just a one-machine, 01:55.640 --> 02:05.280 which is something which has to do some job, but you don't want to interact all the time, 02:05.280 --> 02:12.640 and the main process is done on the SDR itself. 02:12.640 --> 02:19.200 So if you want to interact with this, you just have to get a diagnostic viewer, which 02:19.200 --> 02:30.640 means generally a web browser, which works on every platform, even on the telephone. 02:30.640 --> 02:34.280 So that's here the idea. 02:34.320 --> 02:45.200 So my plan here to demonstrate it is first, what is the pre-to-SDR limits, mainly on the 02:45.200 --> 02:51.680 other side, what the clones are now. 02:51.680 --> 03:03.480 We can find a lot of Chinese clones now, so I try to review that, and after that what is 03:03.520 --> 03:14.000 a firmware, and what is the physical firmware, and it's been after that for autonomous platform, 03:14.000 --> 03:22.400 within mind zero install on the PC, what could be the future, and hopefully have some 03:22.400 --> 03:25.600 question about that. 03:25.600 --> 03:38.360 So as many know what is pre-to-SDR, there is a lot of characteristics, which are not 03:38.360 --> 03:42.680 very easy to over limit. 03:42.680 --> 03:57.680 The first is that the QSP flash, so what contains firmware is only 32MB, so on this flash, 03:57.680 --> 04:06.640 which is on your pre-to-SDR, you need to have the bitstream of the FPGA, the Linux, and 04:06.680 --> 04:08.880 application on that. 04:08.880 --> 04:19.880 So it's quite a little to have all that. 04:19.880 --> 04:28.840 On the link between the PC, because right now we are using the SDR, like a peripheral, so we 04:28.880 --> 04:38.080 need a link between the PC and the P2SDR, and we are limited to USP2 right now, and 04:38.080 --> 04:48.120 getting over three or four megabytes without drop is not always very easy with this USP2. 04:48.120 --> 04:58.440 There is several reasons, it could be a protocol, which is IO, well. 04:58.440 --> 05:03.080 So this is a problem. 05:03.080 --> 05:13.720 If you want to use it as an autonomous platform, then you want to add extra software 05:13.720 --> 05:25.320 in it, because you know that on the P2SDR, you have, of course, the ADC 1973, which is the 05:25.360 --> 05:29.880 analog digital converter and digital analog converter. 05:29.880 --> 05:45.360 You have the FPGA, which is zinc-710, which mainly transfer, well, transfer, the signal from 05:45.360 --> 05:54.280 the analog device to the USB, and on the zinc, there is a little arm in it. 05:54.280 --> 06:06.960 So this processor, which is nearly not used, actually, is like a P Raspberry P2, so not 06:06.960 --> 06:14.200 very powerful, but enough to run some software on it. 06:14.200 --> 06:24.840 The FPGA is only 710, so with the firmware from ADC, it is nearly full. 06:24.840 --> 06:37.480 We can clean some blocks of FPGA, for example, the decimator, an interpreter, or DDS, which 06:37.560 --> 06:46.160 is by default, but we are quite full on the P2SDR itself. 06:46.160 --> 06:48.520 Now what are these clones? 06:48.520 --> 06:53.440 So this is a clone, okay. 06:53.440 --> 06:59.480 It costs about 150 years right now. 06:59.560 --> 07:13.120 It has a GBB internet, so not a GBB internet, two USB, and an SD card. 07:13.120 --> 07:23.000 You can have also a USB debug, which is very useful when you don't know what your 07:23.000 --> 07:27.800 P2SDR is doing. 07:27.840 --> 07:38.040 There is a lot of clone like that, and from many manufacturers. 07:38.040 --> 07:48.760 The many issues with this Chinese clone is we don't know exactly who is the creator of 07:48.760 --> 07:57.520 this clone, which means that if you want to report some bugs, or hardware modification, it's 07:57.560 --> 08:02.320 very complicated to reach a contact on that. 08:02.320 --> 08:13.360 So it's less documented, but cheaper right now compared to an original P2SDR, which is 08:13.360 --> 08:19.040 around 250, I think, right now. 08:19.080 --> 08:31.680 This is from NTSDR, which is one of a clone, where we know exactly the source, and you 08:31.680 --> 08:45.280 see that it's quite comparable to the P2SDR, but you have a bigger FPGM, and you have, okay, 08:45.320 --> 08:57.920 all the RX-12, you have also some clock here, which is deepened, you have a GPIOE 08:57.920 --> 09:04.920 either, which could be very useful. 09:04.920 --> 09:16.120 The clock, okay, this is a clock from, and we spoke about it, a lot of the clock, if you 09:16.120 --> 09:30.060 want to have GPIO synchronization, then you can input a PPS, or 10MF input, that's for the 09:30.060 --> 09:41.980 NTSDR, and the clock is quite good, because you can even input a 40MF clock, or you can use 09:41.980 --> 09:55.140 the FPGM, which control the VCTCXO of your NTSDR, okay, that's a good thing, but on all the 09:55.140 --> 10:06.420 clones, there are some missing parts, which mean that if you want to input 40MF instead 10:06.420 --> 10:13.620 of the standard oscillator, which is on the board, you need to desoldier this and sort 10:13.620 --> 10:28.180 of this, this is very small, so for us, a matter, this CMS is not very easy to use, so 10:28.180 --> 10:41.900 be careful about the external clock, okay, so now we need a firmware in order to, that's 10:41.900 --> 10:51.620 these clones works, at each time the manufacturer could bring you a firmware, but generally 10:51.620 --> 11:02.260 not well maintained, so I decided to support a lot of boards, which have in common that they 11:02.260 --> 11:20.580 have the same architecture, the same FPGM, or smaller bigger, and the same AD, 93 converter, so the 11:20.580 --> 11:35.700 build, the firmware, which is containing first the bootloader, so the U-boot, you have the FPGM inside, 11:35.700 --> 11:46.700 and you have the Linux and the rootFS, okay, so ADI, I was providing a firmware builder, which 11:46.700 --> 11:57.100 is build on build root, but not completely, with some make file, external make file, so I decided 11:57.100 --> 12:10.020 to be 100% build root, so it's very easy to just get build root and make a deaf config and 12:10.020 --> 12:23.180 it's okay, it's based on Linux 6.1, and you have rootFS, so all the application above Linux, 12:23.180 --> 12:36.700 are common above all the bolts, the FPGA is custom FPGA, based on the Maya Zia from Daniel, and with 12:36.700 --> 12:46.860 this firmware, you can write a system file from SD card, which boot from the SD card, or for 12:46.860 --> 12:59.980 the flash, and well, as it's simple to build, we can build it on a GitHub directly, you can build 12:59.980 --> 13:14.020 it yourself, even on Windows with WSL, and it's just open to 22.00 database, and as soon as you 13:14.020 --> 13:29.220 have build your firmware, you just need to add CP it on the right, the USB card, and it's okay, 13:29.220 --> 13:44.260 and the FPGA is side, so there is a new 50 process, so all that is custom FPGA, doesn't consume 13:44.260 --> 13:57.780 anything on the CPU, on the RBCPU of the tutorial Zia, so you have FFT done by Maya Zia, I had 13:57.820 --> 14:08.420 some transformation from complex IQ, normally it's complex IQ size bits, 16 bits, and here 14:08.420 --> 14:19.480 we can choose from 12 to 8 bits, because the native ADC is only 12 bits, so you can have more 14:19.480 --> 14:30.040 bandwidth, well it's it's consuming less bandwidth if you use for example 8 bits, that is 14:30.040 --> 14:46.960 this decimation, so we Daniel just explained what the fear, and the fear from Remes, 14:46.960 --> 14:58.240 just very efficient, and so this decimation going to IO, so it means that even on a classical 14:58.240 --> 15:09.360 application, south-party application, you can get the result of the decimation, and this 15:09.360 --> 15:20.320 is very useful, if for example you want to see the old spectrum, but just want to isolate 15:20.320 --> 15:29.320 only one sub band, you can use this, and without getting all the bandwidth through USB or 15:29.400 --> 15:45.120 it done it, I also had some overclocking based on experiment from other guys in firmware, and 15:45.120 --> 15:58.720 it's quite well, it works quite good, because we can have had to 45 mega-sumble over a gigabits 15:58.800 --> 16:10.160 with this kind of overclocking, so it could be very useful also, I don't know about the 16:10.160 --> 16:21.400 temperature of the FPGA, but well, that's an option, Tesoucai is also handling LVDS, which means 16:21.400 --> 16:33.760 that instead of running CMOS, we can have more bandwidth from the ADC to the FPGA, and 16:33.760 --> 16:47.760 there is the two reception, two transmission supported, the Linux kernel, so it's not directly 16:47.800 --> 16:56.440 Linux, but there is first the U-boot, which is on the SD, and for now we get the root FS so 16:56.440 --> 17:05.480 all the application on the run, so it's the same as before on the previous SDR, and the 17:05.480 --> 17:11.960 device tree is done by board, which means that the Linux is common, and you just have to 17:11.960 --> 17:22.520 describe UDS and build your firmware with that, I had some USB drivers, because generally 17:22.520 --> 17:31.960 if you have a PUTOS DR, you want to make USB to return it, then you can just plug it on USB 17:31.960 --> 17:41.600 and it works, I had them through GPS, audio, and even Wi-Fi, and I extend the frequency, 17:41.600 --> 18:01.200 so generally, ADC, 963 is 3, 350 to 6 GHz, and here I can go down to 47 MHz, so on the root FS, 18:01.200 --> 18:14.040 which means all the application, there is a WTFL server, a possible SWIP, so the SWIP is here, 18:14.040 --> 18:26.880 which means that we have normally max 61 MHz of bandwidth, and with the SWIP, we fast 18:26.880 --> 18:39.280 lock on 8 bands, because the register is only for 8, so it's 60 MHz by 8, so we have here 18:39.280 --> 18:52.120 4 and 80 MHz spectrum, and for the transmission, I just add a PTT on GPIO, which is quite 18:52.120 --> 19:06.120 huge, useful for amateur when they use amplifier, so the third party are already using some 19:06.120 --> 19:17.120 features, and here are some examples on that, the Tezuka community is quite huge now, 19:17.120 --> 19:30.680 there is around 10,000 downloads, a lot of issues, and some contributors, and thanks for that, 19:30.680 --> 19:45.680 there is some manufacturers, and some samples to test on it, maybe a little demo, 19:45.680 --> 20:00.640 I don't know if, yeah, so here you have SDR++ running at, well, all the band, 20:00.640 --> 20:15.640 on the FM, so 80, 28 MHz, and so we can listen to the modulation here on the FM band, 20:15.640 --> 20:29.640 and at the same time we can see it on the web browser, this is a very, well, classical use, 20:29.640 --> 20:53.640 and for the sweep here, we have from 500 to 8, so we have 40, 480 MHz of band, and so here we can see 20:53.640 --> 21:09.640 some GSM, and the firmware is quite good, because we can have to have 5 KHz of Fremorites, so the next one, 21:09.640 --> 21:31.640 for Spectrum, okay, so right now it's just a no more firmware, and now we want to be autonomous, 21:31.640 --> 21:50.640 so instead of having the root FS on the run, we put it on the SD, and that's extend a lot, the application of the Puto, well, 21:50.640 --> 21:56.640 it's not the Puto, because there is no SD on the Puto, but on the clone. 21:56.640 --> 22:09.640 This is a TZUK extension, which means that the Linux kernel is the same as TZUK, and the ZUK in Europe is just a root FS, so just the application of that. 22:09.640 --> 22:33.640 It's deviant to 12-based, so instead of having very little size, we and only build root, then we have deviant to deviant based, so with all the package you want. 22:33.640 --> 22:53.640 It's persistent, which means that it's more easy to make some application on that, the process is just scripts to install several application, which it's used with KMU, 22:53.640 --> 23:08.640 and I have some pretty easy tool, like VNC access with web, so it's no VNC, and the print cell package. 23:08.640 --> 23:18.640 So for example, you can compile on target, wow, it's not always possible, because there is a big project, 23:18.640 --> 23:43.640 but if you want just to compile some very little projects, just you don't need to cross-compile, and you have all the tools on the clone itself, which means that you have GCC, you have already Python 3 installed. 23:43.640 --> 23:58.640 You have new radio, an example from Johnny Shell, from the book, and several other application on that. 23:58.640 --> 24:13.640 And you can see that there is a radio already. The radio is just, it's just odd, and it's integrate just a few hours ago. 24:13.640 --> 24:26.640 And there is remote as they are, so this is a sample of web application, which can be demodulated. 24:26.640 --> 24:54.640 Okay, this is what is, sorry. So this is a web application, okay, and this is done on the, on the tutorial, just on the arm, and you have some new radio script, 24:54.640 --> 25:15.640 running on the print of itself. So the problem is that if I use the original project, there is some very high process. 25:15.640 --> 25:30.640 The first one is the spectrum, not the highest, but we need to compute the FFT from the IQ, and the main is the decimation. 25:30.640 --> 25:48.640 Which means that the arm, the little arm on the print of is not very sippy, well, it's just a little pi-do, pi-do, and so this machine here is around 1 and 20. 25:48.640 --> 25:59.640 So you go from 2.5 or 2.5 mega sample, and you decimate by 120. 25:59.640 --> 26:24.640 So instead of that, we use just 20 here to reduce it. Why? Because we use the SPGA to decimation to make the NCO, so the frequency tuning, and we get the spectrum instead of that. 26:24.640 --> 26:53.640 So all is done on the SPGA, and with that, we can then run it. I can show you some, what, so this is a web interface, okay, 26:53.640 --> 27:18.640 and I connect to my printer. The password is analogs. So this is a new radio working on the printer itself, okay, and then here it's getting the FFT from the FPGA. 27:18.640 --> 27:39.640 We have, for example, Octave, if you want to, well, the idea is to have a match as application on the SDI itself, and you don't have to install it on your PC. 27:39.640 --> 27:55.640 And I don't know, yeah, you can have, so J predict, for example, if you are interesting in satellite, and want to use the Doppler to receive it from the radio. 27:55.640 --> 28:21.640 I know that there is also a GR satellite inside. Here I use, it's a little different from Maya. I just add some overlay, well, it's a proof of concept, just to try to add some features on it. 28:21.640 --> 28:42.640 And this is remote SDR. So with this, maybe we will hear it, I don't know if there is audio. 28:43.640 --> 28:57.640 So all this, on the web interface, you can receive it, and you can make else or some transmission. So some, sorry. 28:57.640 --> 29:12.640 Some, some guys use it to, to transmit on a Q100, okay, because you have a complete receiver here, which works alone. 29:12.640 --> 29:26.640 So you can, you can put your clone on, well, just near your antenna, and then just have a little asymmetry cable, and you have, 29:26.640 --> 29:51.640 you're a transmitter. So the installation is very easy. If you don't want to install all, to yourself, just go to the GitHub of the Conego pair, write it on SD card, because it's a ISO. 29:51.640 --> 30:05.640 So use a Barney Ultra, for example, and then you will have on the boot, civil folder, and one folder is for one border. 30:05.640 --> 30:17.640 So just get the file, which is under this folder, and go to the boot. So there is a readme on that, but I just do that. 30:17.640 --> 30:43.640 And so it could handle several boards with these techniques. Okay, the limits, the limits for this autonomous, is that, well, it's not really agnostic, which means that we, we need to know how the FPGA is working, 30:43.640 --> 31:03.640 and so it's not a classical SDR. Some process could not be done on the arm, and even on the FPGA, well, it could be done, but it's complicated. 31:03.640 --> 31:23.640 For example, if you want to, to a process, a white band with a wham or something like that, if it's not done on the FPGA, then you can do this on your arm, and then you need to get all the bands for you PC. 31:23.640 --> 31:38.640 So, and if you prefer to compute all the IQ of a GPU, then it's not, it's not the target of this project. 31:39.640 --> 31:54.640 Okay, Adi, 96X has already have some limits, especially with the synchronization, and Jean-Michel has just explained us what, what the problem. 31:54.640 --> 32:14.640 We'll see that there is some I-O CPU usage. So, the I-O is the protocol from I-D-I, to go from the, the P2SDR to the PC, and it is a very, very high CPU usage for that. 32:14.640 --> 32:28.640 It's based on RPC, and even you have a lot of bandwidth network, the limitation is the CPU. That's why we try to overclock it. 32:28.640 --> 32:42.640 The solution could be maybe, to have direct, direct implementation from the FPGA, going to the G-Dabbit. 32:42.640 --> 33:05.640 So, what is the future? Maybe having this kind of thing, which is autonomous, which process all the DSP in FPGA, and then use a lighter DSP on the web browser. 33:05.640 --> 33:25.640 So, this could be done with cyber ether. So, if we can get Websook at some of the future SDR, then it could be easily managed by browser with JavaScript, etc. 33:25.640 --> 33:45.640 So, try to have a more FPGA module. I begin to, to refactor the FPGA one, which is where you can add or remove some components. 33:45.640 --> 34:03.640 You are on big FPGA, and you can have more interpolation, you can have, and you can choose the components. So, this is the next one. 34:03.640 --> 34:26.640 This is now with the GPL, and GPL is quite good for the latest clones, because you can use them for discussion with the FPGA, or try to synchronize several balls. 34:26.640 --> 34:42.640 Well, there is, you can, you can extend it to SPI, or I2C if you want to add a lead or a band filter, for example. 34:42.640 --> 35:10.640 Maybe put this to red pizzeria, and for all the people who have a Pluto, but not a clone. What about this project? Well, if I add the possibility to plug a USB on your Pluto, then you will have the same. 35:12.640 --> 35:28.640 So, thank you very much for Daniel, and for the source of the FPGA and the contribution, thanks for the community. 35:28.640 --> 35:35.640 And so, I hope that you enjoyed.